869 search results - page 71 / 174 » Cache Architectures for Reconfigurable Hardware |
LCTRTS
2007
Springer
15 years 4 months ago
2007
Springer
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
86
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FPL
2005
Springer
15 years 3 months ago
2005
Springer
This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial rec...
FCCM
2004
IEEE
15 years 1 months ago
2004
IEEE
General purpose computing architectures are being called on to work on a more diverse application mix every day. This has been fueled by the need for reduced time to market and ec...
103
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HOTI
2005
IEEE
15 years 3 months ago
2005
IEEE
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
ICASSP
2011
IEEE
14 years 1 months ago
2011
IEEE
Decoder architectures for architecture-aware Raptor codes having regular message access-and-processing patterns are presented. Raptor codes are a class of concatenated codes compo...