Sciweavers

869 search results - page 7 / 174
» Cache Architectures for Reconfigurable Hardware
Sort
View
HPCA
2008
IEEE
15 years 12 months ago
An OS-based alternative to full hardware coherence on tiled CMPs
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
Christian Fensch, Marcelo Cintra
FPL
2008
Springer
117views Hardware» more  FPL 2008»
15 years 1 months ago
On-the-fly attestation of reconfigurable hardware
This paper presents a novel method to perform on-the-fly attestation of hardware structures loaded to reconfigurable devices. Given that a loadable hardware structure to a reconfi...
Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa
ASPDAC
2008
ACM
164views Hardware» more  ASPDAC 2008»
15 years 1 months ago
The Shining embedded system design methodology based on self dynamic reconfigurable architectures
Complex design, targeting System-on-Chip based on reconfigurable architectures, still lacks a generalized methodology allowing both the automatic derivation of a complete system s...
Carlo Curino, Luca Fossati, Vincenzo Rana, Frances...
ERSA
2009
147views Hardware» more  ERSA 2009»
14 years 9 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias