We are attacking the memory bottleneck by building a “smart” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting appl...
Binu K. Mathew, Sally A. McKee, John B. Carter, Al...
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
We propose and analyze an information-sharing application for wireless intervehicular networks, called Infoshare. Infoshare leverages the broadcast nature of the wireless medium t...
Marco Fiore, Claudio Casetti, Carla-Fabiana Chiass...
An accurate cost-model that accounts for dataset size and structure can help optimize geoscience data analysis. We develop and apply a computational model to estimate data analysi...
Modern shared-memory multiprocessors use complex memory system implementations that include a variety of non-trivial and interacting optimizations. More time is spent in verifying...
Manoj Plakal, Daniel J. Sorin, Anne Condon, Mark D...