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MICRO
2007
IEEE
129views Hardware» more  MICRO 2007»
15 years 10 months ago
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
Jason Zebchuk, Elham Safi, Andreas Moshovos
IPSN
2007
Springer
15 years 10 months ago
Harbor: software-based memory protection for sensor nodes
Many sensor nodes contain resource constrained microcontrollers where user level applications, operating system components, and device drivers share a single address space with no...
Ram Kumar, Eddie Kohler, Mani B. Srivastava
SIGSOFT
2006
ACM
15 years 10 months ago
Bit level types for high level reasoning
Bitwise operations are commonly used in low-level systems code to access multiple data fields that have been packed into a single word. Program analysis tools that reason about s...
Ranjit Jhala, Rupak Majumdar
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
15 years 9 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
163
Voted
ER
2005
Springer
200views Database» more  ER 2005»
15 years 9 months ago
How to Tame a Very Large ER Diagram (Using Link Analysis and Force-Directed Drawing Algorithms)
Abstract. Understanding a large schema without the assistance of persons already familiar with it (and its associated applications), is a hard and very time consuming task that occ...
Yannis Tzitzikas, Jean-Luc Hainaut