347 search results - page 15 / 70 » Caching processor general registers |
109
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CASES
2005
ACM
14 years 11 months ago
2005
ACM
Code compression is a field where compression ratios between compiler-generated code and subsequent compressed code are highly dependent on decisions made at compile time. Most op...
101
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PLDI
2006
ACM
15 years 3 months ago
2006
ACM
This paper describes a global progressive register allocator, a register allocator that uses an expressive model of the register allocation problem to quickly find a good allocat...
CODES
2010
IEEE
14 years 7 months ago
2010
IEEE
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for generalpurpos...
SC
2009
ACM
15 years 4 months ago
2009
ACM
The management of shared caches in multicore processors is a critical and challenging task. Many hardware and OS-based methods have been proposed. However, they may be hardly adop...
DSN
2002
IEEE
15 years 2 months ago
2002
IEEE
The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32-bit processor based on the SPARC V8 instruction set. The processors toler...