347 search results - page 18 / 70 » Caching processor general registers |
FSE
2006
Springer
15 years 1 months ago
2006
Springer
This paper studies the state-of-the-art software optimization methodology for symmetric cryptographic primitives on the new 64-bit x64 processors, AMD Athlon64 (AMD64) and Intel Pe...
XIMEP
2006
ACM
15 years 3 months ago
2006
ACM
We present a high-performance, pull-based streaming processor for XQuery, called XQPull, that can handle many essential features of the language, including general predicates, rec...
CODES
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
81
Voted
CASES
2006
ACM
15 years 3 months ago
2006
ACM
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...