347 search results - page 24 / 70 » Caching processor general registers |
143
click to vote
MICRO
2000
IEEE
14 years 9 months ago
2000
IEEE
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
DAC
2010
ACM
14 years 9 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
121
click to vote
IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
88
Voted
DSN
2008
IEEE
14 years 11 months ago
2008
IEEE
CMOS technology trends are leading to an increasing incidence of hard (permanent) faults in processors. These faults may be introduced at fabrication or occur in the field. Wherea...
82
Voted
VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...