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» Caching processor general registers
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81
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ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 11 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner
98
Voted
CASES
2005
ACM
14 years 11 months ago
Exploiting pipelining to relax register-file port constraints of instruction-set extensions
Customisable embedded processors are becoming available on the market, thus making it possible for designers to speed up execution of applications by using Application-specific F...
Laura Pozzi, Paolo Ienne
ISCA
1996
IEEE
130views Hardware» more  ISCA 1996»
15 years 1 months ago
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
Mark Horowitz, Margaret Martonosi, Todd C. Mowry, ...
SAMOS
2007
Springer
15 years 3 months ago
A Study of Energy Saving in Customizable Processors
Abstract. Embedded systems are special purpose systems which perform predefined tasks with very specific requirements like high performance, low volume or low power. Most of the ...
Paolo Bonzini, Dilek Harmanci, Laura Pozzi
76
Voted
ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
15 years 4 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...