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» Caching processor general registers
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SBCCI
2005
ACM
115views VLSI» more  SBCCI 2005»
15 years 3 months ago
Design of a decompressor engine on a SPARC processor
Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumpti...
Richard E. Billo, Rodolfo Azevedo, Guido Araujo, P...
CCGRID
2010
IEEE
14 years 8 months ago
An Adaptive Data Prefetcher for High-Performance Processors
—While computing speed continues increasing rapidly, data-access technology is lagging behind. Data-access delay, not the processor speed, becomes the leading performance bottlen...
Yong Chen, Huaiyu Zhu, Xian-He Sun
CF
2006
ACM
15 years 3 months ago
Improving the memory behavior of vertical filtering in the discrete wavelet transform
The discrete wavelet transform (DWT) is used in several image and video compression standards, in particular JPEG2000. A 2D DWT consists of horizontal filtering along the rows fo...
Asadollah Shahbahrami, Ben H. H. Juurlink, Stamati...
AINA
2007
IEEE
15 years 4 months ago
Synthetic Trace-Driven Simulation of Cache Memory
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
Rahman Hassan, Antony Harris, Nigel P. Topham, Ari...
ISLPED
2003
ACM
95views Hardware» more  ISLPED 2003»
15 years 2 months ago
Power efficient comparators for long arguments in superscalar processors
Traditional pulldown comparators that are used to implement associativeaddressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the co...
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad ...