347 search results - page 41 / 70 » Caching processor general registers |
106
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CASES
2007
ACM
15 years 1 months ago
2007
ACM
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...
74
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MICRO
2010
IEEE
14 years 7 months ago
2010
IEEE
Recently-proposed architectures that continuously operate on atomic blocks of instructions (also called chunks) can boost the programmability and performance of shared-memory mult...
WDAG
1995
Springer
15 years 1 months ago
1995
Springer
This paper proposes a general definition of self-stabilizing wait-free shared memory objects. The definition ensures that, even in the face of processor failures, every executio...
CASES
2009
ACM
14 years 7 months ago
2009
ACM
In this paper we address the issue of making a program reversible in terms of spatial complexity. Spatial complexity is the amount of memory/register locations required for perfor...
169
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FPGA
2011
ACM
14 years 1 months ago
2011
ACM
As soft processors are increasingly used in diverse applications, there is a need to evolve their microarchitectures in a way that suits the FPGA implementation substrate. This pa...