347 search results - page 45 / 70 » Caching processor general registers |
162
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ASPLOS
2009
ACM
15 years 10 months ago
2009
ACM
Miss rate curves (MRCs) are useful in a number of contexts. In our research, online L2 cache MRCs enable us to dynamically identify optimal cache sizes when cache-partitioning a s...
106
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CODES
2004
IEEE
15 years 1 months ago
2004
IEEE
There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area i...
185
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GLVLSI
2011
IEEE
14 years 1 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
COMPUTER
1998
14 years 9 months ago
1998
Much of a computer’s value depends on how well it interacts with networks. To enhance this value, designers must improve the performance of networks delivered to users. Fortunat...
ICS
2003
Tsinghua U.
15 years 2 months ago
2003
Tsinghua U.
Cache behavior modeling is an important part of modern optimizing compilers. In this paper we present a method to estimate the number of cache misses, at compile time, using a mac...