347 search results - page 46 / 70 » Caching processor general registers |
85
Voted
ISCA
2010
IEEE
15 years 2 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
ICS
1999
Tsinghua U.
15 years 1 months ago
1999
Tsinghua U.
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...
ICS
2004
Tsinghua U.
15 years 3 months ago
2004
Tsinghua U.
We propose a novel replacement algorithm, called InterReference Gap Distribution Replacement (IGDR), for setassociative secondary caches of processors. IGDR attaches a weight to e...
92
Voted
ISCA
2009
IEEE
15 years 4 months ago
2009
IEEE
The advent of multicores has introduced new challenges for programmers to provide increased performance and software reliability. There has been significant interest in technique...
89
Voted
CASES
2010
ACM
14 years 7 months ago
2010
ACM
Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all ...