347 search results - page 47 / 70 » Caching processor general registers |
90
Voted
IWMM
1998
Springer
15 years 1 months ago
1998
Springer
Stoye's one-bit reference tagging scheme can be extended to local counts of two or more via two strategies. The first, suited to pure register transactions, is a cache of ref...
78
Voted
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...
ISCA
1998
IEEE
15 years 1 months ago
1998
IEEE
Most large shared-memory multiprocessors use directory protocols to keep per-processor caches coherent. Some memory references in such systems, however, suffer long latencies for ...
ISCA
2009
IEEE
15 years 4 months ago
2009
IEEE
Detecting data races in parallel programs is important for both software development and production-run diagnosis. Recently, there have been several proposals for hardware-assiste...
LCTRTS
2009
Springer
15 years 4 months ago
2009
Springer
Register allocation is often a two-phase approach: spilling of registers to memory, followed by coalescing of registers. Extreme liverange splitting (i.e. live-range splitting aft...