347 search results - page 48 / 70 » Caching processor general registers |
CODES
2009
IEEE
15 years 2 months ago
2009
IEEE
Reconfigurable Processors utilize a reconfigurable fabric (to implement application-specific accelerators) and may perform runtime reconfigurations to exchange the set of deployed...
IEEEPACT
2007
IEEE
15 years 4 months ago
2007
IEEE
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
106
Voted
EXPCS
2007
15 years 1 months ago
2007
Context switching imposes a performance penalty on threads in a multitasking environment. The source of this penalty is both direct overhead due to running the context switch code...
IEEEPACT
2006
IEEE
15 years 3 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
79
Voted
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Correctness is a paramount attribute of any microprocessor design; however, without novel technologies to tame the increasing complexity of design verification, the amount of bugs...