Sciweavers

347 search results - page 52 / 70
» Caching processor general registers
Sort
View
EXPCS
2007
14 years 11 months ago
Pipeline spectroscopy
Pipeline Spectroscopy is a new technique that allows us to measure the cost of each cache miss. The cost of a miss is displayed (graphed) as a histogram, which represents a precis...
Thomas R. Puzak, Allan Hartstein, Philip G. Emma, ...
IWMM
2009
Springer
152views Hardware» more  IWMM 2009»
15 years 4 months ago
A new approach to parallelising tracing algorithms
Tracing algorithms visit reachable nodes in a graph and are central to activities such as garbage collection, marshalling etc. Traditional sequential algorithms use a worklist, re...
Cosmin E. Oancea, Alan Mycroft, Stephen M. Watt
103
Voted
MICRO
2003
IEEE
258views Hardware» more  MICRO 2003»
15 years 2 months ago
LLVA: A Low-level Virtual Instruction Set Architecture
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
Vikram S. Adve, Chris Lattner, Michael Brukman, An...
IEEEPACT
2000
IEEE
15 years 2 months ago
The Effect of Code Reordering on Branch Prediction
Branch prediction accuracy is a very important factor for superscalarprocessor performance. The ability topredict the outcome of a branch allows the processor to effectively use a...
Alex Ramírez, Josep-Lluis Larriba-Pey, Mate...
ISCA
2002
IEEE
104views Hardware» more  ISCA 2002»
14 years 9 months ago
Speculative Dynamic Vectorization
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
Alex Pajuelo, Antonio González, Mateo Valer...