347 search results - page 57 / 70 » Caching processor general registers |
CODES
2005
IEEE
15 years 3 months ago
2005
IEEE
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
ANCS
2007
ACM
15 years 1 months ago
2007
ACM
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
SIGMETRICS
2005
ACM
15 years 3 months ago
2005
ACM
The running time of many applications is dominated by the cost of memory operations. To optimize such applications for a given platform, it is necessary to have a detailed knowled...
CODES
2007
IEEE
15 years 4 months ago
2007
IEEE
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
STOC
2004
ACM
15 years 10 months ago
2004
ACM
The Collect problem for an asynchronous shared-memory system has the objective for the processors to learn all values of a collection of shared registers, while minimizing the tot...