347 search results - page 60 / 70 » Caching processor general registers |
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CODES
2009
IEEE
15 years 4 months ago
2009
IEEE
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
ISCA
2007
IEEE
15 years 3 months ago
2007
IEEE
Server consolidation is becoming an increasingly popular technique to manage and utilize systems. This paper develops CMP memory systems for server consolidation where most sharin...
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ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
Modern processors can issue and execute multiple instructions per cycle, often performing multiple memory operations simultaneously. To reduce stalls due to resource conflicts, m...
ISCA
2010
IEEE
15 years 2 months ago
2010
IEEE
Light-weight, flexible access control, which allows software to regulate reads and writes to any granularity of memory region, can help improve the reliability of today’s multi...
DAC
2003
ACM
15 years 2 months ago
2003
ACM
This paper presents an analytical framework for the implementation of digital infinite impulse response filters in fixed-point hardware on field programmable gate arrays. This ana...