347 search results - page 62 / 70 » Caching processor general registers |
ASPLOS
2010
ACM
15 years 4 months ago
2010
ACM
DRAM is facing severe scalability challenges in sub-45nm technology nodes due to precise charge placement and sensing hurdles in deep-submicron geometries. Resistive memories, suc...
68
Voted
BTW
2007
Springer
15 years 3 months ago
2007
Springer
B-tree and index into two layers of abstraction. In addition, this paper provides algorithms for (i) concurrency control and recovery including locking of individual keys and of co...
101
click to vote
ACMMSP
2005
ACM
15 years 3 months ago
2005
ACM
In general-purpose applications, most data is dynamically allocated. The memory manager therefore plays a crucial role in application performance by determining the spatial locali...
77
Voted
ISCA
1997
IEEE
15 years 1 months ago
1997
IEEE
As processor architectures have increased their reliance on speculative execution to improve performance, the importance of accurate prediction of what to execute speculatively ha...
CASES
2007
ACM
15 years 1 months ago
2007
ACM
In this paper we describe the design and implementation of a flexible, and extensible, just-in-time ARM simulator designed to run co-operatively with a multi-core DSP simulator on...