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» Caching queues in memory buffers
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DATE
2000
IEEE
101views Hardware» more  DATE 2000»
15 years 2 months ago
Memory Arbitration and Cache Management in Stream-Based Systems
With the ongoing advancements in VLSI technology, the performance of an embedded system is determined to a large extend by the communication of data and instructions. This results...
Françoise Harmsze, Adwin H. Timmer, Jef L. ...
ISORC
2000
IEEE
15 years 2 months ago
TCP Throughput and Buffer Management
There have been many debates about the feasibility of providing guaranteed Quality of Service (QoS) when network traffic travels beyond the enterprise domain and into the vast unk...
Todd Lizambri, Fernando Duran, Shukri Wakid
ICPP
2006
IEEE
15 years 3 months ago
Data Transfers between Processes in an SMP System: Performance Study and Application to MPI
— This paper focuses on the transfer of large data in SMP systems. Achieving good performance for intranode communication is critical for developing an efficient communication s...
Darius Buntinas, Guillaume Mercier, William Gropp
MICRO
2005
IEEE
110views Hardware» more  MICRO 2005»
15 years 3 months ago
Scalable Store-Load Forwarding via Store Queue Index Prediction
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
Tingting Sha, Milo M. K. Martin, Amir Roth
HOTI
2005
IEEE
15 years 3 months ago
Design of Randomized Multichannel Packet Storage for High Performance Routers
High performance routers require substantial amounts of memory to store packets awaiting transmission, requiring the use of dedicated memory devices with the density and capacity ...
Sailesh Kumar, Patrick Crowley, Jonathan S. Turner