169 search results - page 15 / 34 » Caching queues in memory buffers |
SC
2004
ACM
15 years 3 months ago
2004
ACM
Large datasets, on the order of GB and TB, are increasingly common as abundant computational resources allow practitioners to collect, produce and store data at higher rates. As d...
HPCA
1998
IEEE
15 years 1 months ago
1998
IEEE
Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction level parallelism during the execution of a sequential program. Such ambiguous ...
HPCA
1998
IEEE
15 years 1 months ago
1998
IEEE
The explosive growth in the performance of microprocessors and networks has created a new opportunity to reduce the latency of fine-grain communication. Microprocessor clock speed...
120
Voted
IEEEPACT
2009
IEEE
14 years 7 months ago
2009
IEEE
Abstract--Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current...
75
Voted
CONCURRENCY
2006
14 years 9 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...