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» Caching queues in memory buffers
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ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
14 years 1 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
68
Voted
IPPS
1999
IEEE
15 years 1 months ago
Linear Aggressive Prefetching: A Way to Increase the Performance of Cooperative Caches
Cooperative caches offer huge amounts of caching memory that is not always used as well as it could be. We might find blocks in the cache that have not been requested for many hou...
Toni Cortes, Jesús Labarta
SIGMOD
1992
ACM
111views Database» more  SIGMOD 1992»
15 years 1 months ago
Performance Evaluation of Extended Storage Architectures for Transaction Processing
: The use of non-volatile semiconductor memory within an extended storage hierarchy promises significant performance improvements for transaction processing. Although page-addressa...
Erhard Rahm
69
Voted
SIGGRAPH
1999
ACM
15 years 1 months ago
Optimization of Mesh Locality for Transparent Vertex Caching
Bus traffic between the graphics subsystem and memory can become a bottleneck when rendering geometrically complex meshes. In this paper, we investigate the use of vertex caching...
Hugues Hoppe
MICRO
2006
IEEE
103views Hardware» more  MICRO 2006»
15 years 3 months ago
NoSQ: Store-Load Communication without a Store Queue
This paper presents NoSQ (short for No Store Queue), a microarchitecture that performs store-load communication without a store queue and without executing stores in the outof-ord...
Tingting Sha, Milo M. K. Martin, Amir Roth