169 search results - page 22 / 34 » Caching queues in memory buffers |
CN
2008
14 years 9 months ago
2008
This paper proposes a novel Internet Protocol (IP) packet forwarding architecture for IP routers. This architecture is comprised of a non-blocking Multizone Pipelined Cache (MPC) ...
87
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HPCA
2005
IEEE
15 years 10 months ago
2005
IEEE
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
IWNAS
2006
IEEE
15 years 3 months ago
2006
IEEE
RDMA reduces network latency by eliminating unnecessary copies from network interface cards to application buffers, but how to reduce memory registration cost is a challenge. Prev...
102
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ASPLOS
2010
ACM
15 years 28 days ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
100
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EXPCS
2007
14 years 11 months ago
2007
Pipeline Spectroscopy is a new technique that allows us to measure the cost of each cache miss. The cost of a miss is displayed (graphed) as a histogram, which represents a precis...