169 search results - page 33 / 34 » Caching queues in memory buffers |
ALGORITHMICA
2005
13 years 6 months ago
2005
An optimal prefetching and I/O scheduling algorithm L-OPT, for parallel I/O systems, using a read-once model of block references is presented. The algorithm uses knowledge of the n...
COMCOM
2002
13 years 6 months ago
2002
Abstract-We propose a new webserver architecture optimized for delivery of large, popular files. Delivery of such files currently pose a scalability problem for conventional conten...
HPCA
2007
IEEE
14 years 6 months ago
2007
IEEE
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
IPPS
2008
IEEE
14 years 21 days ago
2008
IEEE
Pipelined SRAM-based algorithmic solutions have become competitive alternatives to TCAMs (ternary content addressable memories) for high throughput IP lookup. Multiple pipelines c...
HPCA
2005
IEEE
14 years 6 months ago
2005
IEEE
Long-latency loads are critical in today's processors due to the ever-increasing speed gap with memory. Not only do these loads block the execution of dependent instructions,...