169 search results - page 5 / 34 » Caching queues in memory buffers |
RTCSA
2008
IEEE
15 years 4 months ago
2008
IEEE
The demand for real-time data services in embedded systems is increasing. In these new computing platforms, using traditional buffer management schemes, whose goal is to minimize ...
HPCA
1997
IEEE
15 years 1 months ago
1997
IEEE
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
FTDCS
1999
IEEE
15 years 1 months ago
1999
IEEE
The impact of buffer management and priority scheduling is examined in stressful scenarios when the aggregate incoming traffic is higher than the output link capacity of an Asynch...
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processo...
ISCA
1994
IEEE
15 years 1 months ago
1994
IEEE
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...