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WMPI
2004
ACM
15 years 3 months ago
Addressing mode driven low power data caches for embedded processors
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
Ramesh V. Peri, John Fernando, Ravi Kolagotla
ICDE
2007
IEEE
125views Database» more  ICDE 2007»
15 years 3 months ago
Improved Buffer Size Adaptation through Cache/Controller Coupling
Database workloads seldom remain static. A system tuned by an expert for the current environment, might not always remain optimal. To deal with this situation, database systems ha...
Christian A. Lang, Bishwaranjan Bhattacharjee, Tim...
GLOBECOM
2009
IEEE
15 years 4 months ago
Emulation of Optical PIFO Buffers
—With recent advances in optical technology, we are closer to building all-optical routers than ever before. A major problem in this area, however, is the lack of all-optical mem...
Houman Rastegarfar, Monia Ghobadi, Yashar Ganjali
ISCA
1994
IEEE
88views Hardware» more  ISCA 1994»
15 years 1 months ago
A Unified Architectural Tradeoff Methodology
Wepresentaunijiedapp?'each to assess thet7adeoff of architecture techniques that affect mean memory access time. The architectural features we consider inciude cache hit Tati...
Chung-Ho Chen, Arun K. Somani
ICCD
1999
IEEE
122views Hardware» more  ICCD 1999»
15 years 1 months ago
Design and Evaluation of a Selective Compressed Memory System
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim