Sciweavers

1415 search results - page 139 / 283
» Can Parallel Algorithms Enhance Serial Implementation
Sort
View
ACSC
2004
IEEE
15 years 6 months ago
Reducing Register Pressure Through LAER Algorithm
When modern processors keep increasing the instruction window size and the issue width to exploit more instruction-level parallelism (ILP), the demand of larger physical register ...
Gao Song
95
Voted
ICPP
2008
IEEE
15 years 8 months ago
On Clustering Tasks in IC-Optimal Dags
Strategies are developed for “fattening” the tasks of computation-dags so as to accommodate the heterogeneity of remote clients in Internet-based computing (IC). Earlier work ...
Mark Sims, Gennaro Cordasco, Arnold L. Rosenberg
113
Voted
IPPS
2006
IEEE
15 years 8 months ago
Aligning traces for performance evaluation
For many performance analysis problems, the ability to reason across traces is invaluable. However, due to non-determinism in the OS and virtual machines, even two identical runs ...
Todd Mytkowicz, Amer Diwan, Matthias Hauswirth, Pe...
101
Voted
SPAA
2010
ACM
15 years 7 months ago
Lightweight, robust adaptivity for software transactional memory
When a program uses Software Transactional Memory (STM) to synchronize accesses to shared memory, the performance often depends on which STM implementation is used. Implementation...
Michael F. Spear
93
Voted
IJNSEC
2006
80views more  IJNSEC 2006»
15 years 2 months ago
Authenticated Access to Reserved Network Resources
Enhanced network services often involve preferential allocation of resources such as transmission capacity ("bandwidth") and buffer space to packets belonging to certain...
Kenneth L. Calvert, Srinivasan Venkatraman, Jim Gr...