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DAC
2003
ACM
16 years 5 months ago
Coverage directed test generation for functional verification using bayesian networks
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
Shai Fine, Avi Ziv
DAC
2003
ACM
16 years 5 months ago
Learning from BDDs in SAT-based bounded model checking
Bounded Model Checking (BMC) based on Boolean Satisfiability (SAT) procedures has recently gained popularity as an alternative to BDD-based model checking techniques for finding b...
Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Ya...
DAC
2003
ACM
16 years 5 months ago
Symbolic representation with ordered function templates
Binary Decision Diagrams (BDDs) often fail to exploit sharing between Boolean functions that differ only in their support variables. In a memory circuit, for example, the function...
Amit Goel, Gagan Hasteer, Randal E. Bryant
DAC
2003
ACM
16 years 5 months ago
Embedded intelligent SRAM
Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage. We present an enhancement called Intelligent SRAM (ISRAM) that co...
Prabhat Jain, G. Edward Suh, Srinivas Devadas
DAC
2003
ACM
16 years 5 months ago
A complexity effective communication model for behavioral modeling of signal processing applications
In this paper, we argue that the address space of memory regions that participate in inter task communication is over-specified by the traditional communication models used in beh...
M. N. V. Satya Kiran, M. N. Jayram, Pradeep Rao, S...