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ISCAS
2006
IEEE
82views Hardware» more  ISCAS 2006»
15 years 9 months ago
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing
– This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that crosscapacitances are ...
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
15 years 8 months ago
Low-power fanout optimization using multiple threshold voltage inverters
This paper addresses the problem of low-power fanout optimization with multiple threshold voltage inverters. Introducing splitting and merging conversions that preserve delay, pow...
Behnam Amelifard, Farzan Fallah, Massoud Pedram
DFT
2003
IEEE
114views VLSI» more  DFT 2003»
15 years 8 months ago
CodSim -- A Combined Delay Fault Simulator
Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this ...
Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, We...
DATE
2002
IEEE
102views Hardware» more  DATE 2002»
15 years 8 months ago
Library Compatible Ceff for Gate-Level Timing
Accurate gate-level static timing analysis in the presence of RC loads has become an important problem for modern deep-submicron designs. Non-capacitive loads are usually analyzed...
Bernard N. Sheehan
DAC
2000
ACM
15 years 7 months ago
Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments
This paper develops the noise-counterparts to familiar delay formulas like Elmore or PRIMO. By matching the first few moments of the network’s transfer impedance, we obtain effi...
Bernard N. Sheehan