This paper presents an approach to build and visualize traceability links and properties of a set of OO software releases. The process recovers an "as is" design from C+...
Giuliano Antoniol, Gerardo Canfora, Andrea De Luci...
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...
Graham Hetherington, Tony Fryars, Nagesh Tamarapal...
This paper reports on an effort to use both the system theoretic DEVS (discrete event simulation) formalism and the JavaBeans component model as a basis for a componentbased discr...
Herbert Praehofer, Johannes Sametinger, Alois Stri...