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177
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TACAS
1998
Springer
15 years 10 months ago
1998
Springer
In this paper, we report on an application of the validation and veri cation tool kit Uppaal in the design and analysis of a prototype gear controller, carried out in a joint proje...
177
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ISMVL
1997
IEEE
15 years 10 months ago
1997
IEEE
This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01)asynchronous circuits. It is shown that fully DIasynchronous cir...
199
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ANZIIS
1996
IEEE
15 years 10 months ago
1996
IEEE
This paper describes the design and developmentof an expert system for tourist information center. The expert system was built to recommend a suitable travel schedule that satisfi...
179
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ISCA
1996
IEEE
15 years 10 months ago
1996
IEEE
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
161
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MICRO
1996
IEEE
15 years 10 months ago
1996
IEEE
Much of the previous work on modulo scheduling has targeted numeric programs, in which, often, the majority of the loops are well-behaved loop-counter-based loops without early ex...