852 search results - page 100 / 171 » Categories, Allegories and Circuit Design |
ISPD
2003
ACM
15 years 5 months ago
2003
ACM
A block-level placement and routing scheme called Fishbone is presented. The routing uses a two-layer spine topology. The pin locations are configurable and restricted to certain ...
GLVLSI
2010
IEEE
15 years 4 months ago
2010
IEEE
This paper presents a self-compensation scheme of manufacturing variability for clock skew reduction. In the proposed scheme, a CDN with embedded variability sensors tunes variabl...
111
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DAC
2004
ACM
15 years 3 months ago
2004
ACM
This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests ...
120
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DAC
2008
ACM
15 years 1 months ago
2008
ACM
The performance advantages in parallel ring-based VCOs are explored. When the number of VCOs is doubled, the parallel VCOs enhance phase noise by 3dB, and the within-chip process-...
GLVLSI
2007
IEEE
15 years 1 months ago
2007
IEEE
Nanoscale crossbars built from nanowires can form high density memories and programmable logic devices. To integrate such nanoscale devices with other circuits, nanowire decoders ...