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ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
15 years 5 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
15 years 3 months ago
A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops
he abstract and simple computation and communication mechanism in the synchronous computational model it is easy to simulate synchronous systems and to apply formal verification m...
Tarvo Raudvere, Ingo Sander, Axel Jantsch
ISPD
2007
ACM
116views Hardware» more  ISPD 2007»
15 years 1 months ago
A morphing approach to address placement stability
Traditionally, research in global placement has focused on relatively few simple metrics, such as pure wirelength or routability estimates. However, in the real world today, desig...
Philip Chong, Christian Szegedy
ISLPED
2010
ACM
193views Hardware» more  ISLPED 2010»
15 years 3 days ago
PASAP: power aware structured ASIC placement
Structured ASICs provide an exciting middle ground between FPGA and ASIC design methodologies. Compared to ASIC, structured ASIC based designs require lower non recurring engineer...
Ashutosh Chakraborty, David Z. Pan
CCS
2010
ACM
15 years 3 days ago
TASTY: tool for automating secure two-party computations
Secure two-party computation allows two untrusting parties to jointly compute an arbitrary function on their respective private inputs while revealing no information beyond the ou...
Wilko Henecka, Stefan Kögl, Ahmad-Reza Sadegh...