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» Categories, Allegories and Circuit Design
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82
Voted
DAC
2007
ACM
15 years 10 months ago
Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors
Three-Dimensional integration provides a simultaneous improvement in wire-related delay and power consumption of microprocessor circuits. Prior work has looked at the performance,...
Kiran Puttaswamy, Gabriel H. Loh
70
Voted
GLVLSI
2005
IEEE
152views VLSI» more  GLVLSI 2005»
15 years 3 months ago
A high speed and leakage-tolerant domino logic for high fan-in gates
Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose a new domino circuit for high fan-in ...
Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peirav...
83
Voted
DAC
2005
ACM
14 years 11 months ago
Piece-wise approximations of RLCK circuit responses using moment matching
Capturing RLCK circuit responses accurately with existing model order reduction (MOR) techniques is very expensive. Direct metrics for fast analysis of RC circuits exist but there...
Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu
65
Voted
GLVLSI
2007
IEEE
115views VLSI» more  GLVLSI 2007»
15 years 3 months ago
Novel architectures for efficient (m, n) parallel counters
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
Sreehari Veeramachaneni, Lingamneni Avinash, Kirth...
ICCAD
2009
IEEE
159views Hardware» more  ICCAD 2009»
14 years 7 months ago
First steps towards SAT-based formal analog verification
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips...