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DAC
2008
ACM
15 years 10 months ago
Bounded-lifetime integrated circuits
Integrated circuits with bounded lifetimes can have many business advantages. We give some simple examples of m ods to enforce tunable expiration dates for chips using nanom reliab...
Puneet Gupta, Andrew B. Kahng
GLVLSI
2010
IEEE
138views VLSI» more  GLVLSI 2010»
15 years 2 months ago
Methodology to achieve higher tolerance to delay variations in synchronous circuits
A methodology is proposed for designing robust circuits exhibiting higher tolerance to process and environmental variations. This higher tolerance is achieved by exploiting the in...
Emre Salman, Eby G. Friedman
DAC
2003
ACM
15 years 10 months ago
Parameter variations and impact on circuits and microarchitecture
Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors. In this paper, we discuss process, voltag...
Shekhar Borkar, Tanay Karnik, Siva Narendra, James...
DAC
2002
ACM
15 years 10 months ago
Petri net modeling of gate and interconnect delays for power estimation
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
Ashok K. Murugavel, N. Ranganathan
GLVLSI
2003
IEEE
219views VLSI» more  GLVLSI 2003»
15 years 2 months ago
Buffer sizing for minimum energy-delay product by using an approximating polynomial
This paper first presents an accurate and efficient method of estimating the short circuit energy dissipation and the output transition time of CMOS buffers. Next the paper descri...
Chang Woo Kang, Soroush Abbaspour, Massoud Pedram