In this paper, we describe an accurate metric (perimeter-degree) for measuring interconnection complexity and effective use of it for controlling congestion in a multilevel framew...
Navaratnasothie Selvakkumaran, Phiroze N. Parakh, ...
We propose a parallel global routing algorithm that concurrently processes routing subproblems corresponding to rectangular subregions covering the chip area. The algorithm uses a...
Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Future multicore processors will be more susceptible to a variety of hardware failures. In particular, intermittent faults, caused in part by manufacturing, thermal, and voltage v...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...
In this paper, we propose fast and efficient techniques to analyze the power grid with accurate modeling of the transistor network. The solution techniques currently available for...
Anand Ramalingam, Giri Devarayanadurg, David Z. Pa...