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EMSOFT
2004
Springer
15 years 3 months ago
A methodology for generating verified combinatorial circuits
High-level programming languages offer significant expressivity but provide little or no guarantees about resource use. Resourcebounded languages -- such as hardware-description l...
Oleg Kiselyov, Kedar N. Swadi, Walid Taha
ISPD
2010
ACM
224views Hardware» more  ISPD 2010»
15 years 6 months ago
An analytical placer for mixed-size 3D placement
Existing 3D placement techniques are mainly used for standardcell circuits, while mixed-size placement is needed to support highlevel functional units and intellectual property (I...
Jason Cong, Guojie Luo
DAC
2003
ACM
15 years 5 months ago
Fast timing-driven partitioning-based placement for island style FPGAs
In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement...
Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
DAC
2005
ACM
16 years 24 days ago
Power emulation: a new paradigm for power estimation
In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the obser...
Joel Coburn, Srivaths Ravi, Anand Raghunathan
ISPD
2003
ACM
73views Hardware» more  ISPD 2003»
15 years 5 months ago
Research directions for coevolution of rules and routers
Design rules in advanced IC manufacturing processes are increasingly problematic for modern router architectures and algorithms. This paper first reviews types and causes of “d...
Andrew B. Kahng