852 search results - page 53 / 171 » Categories, Allegories and Circuit Design |
111
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GLVLSI
2008
IEEE
15 years 6 months ago
2008
IEEE
With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the ...
GLVLSI
2007
IEEE
15 years 3 months ago
2007
IEEE
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
IOLTS
2005
IEEE
15 years 5 months ago
2005
IEEE
Selecting a strong cryptographic algorithm makes no sense if the information leaks out of the device through sidechannels. Sensitive information, such as secret keys, can be obtai...
101
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FPGA
2010
ACM
15 years 8 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
120
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CODES
2005
IEEE
15 years 5 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...