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FPGA
2003
ACM
154views FPGA» more  FPGA 2003»
15 years 5 months ago
Parallel placement for field-programmable gate arrays
Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). In this paper, we ...
Pak K. Chan, Martine D. F. Schlag
DAC
2010
ACM
15 years 3 months ago
Eyecharts: constructive benchmarking of gate sizing heuristics
—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard ...
Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla...
DAC
2007
ACM
16 years 25 days ago
Physical Unclonable Functions for Device Authentication and Secret Key Generation
Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that...
G. Edward Suh, Srinivas Devadas
DAC
2006
ACM
16 years 24 days ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
GLVLSI
2005
IEEE
199views VLSI» more  GLVLSI 2005»
15 years 5 months ago
Interconnect delay minimization through interlayer via placement in 3-D ICs
The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via lo...
Vasilis F. Pavlidis, Eby G. Friedman