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ISLPED
2003
ACM
80views Hardware» more  ISLPED 2003»
15 years 5 months ago
Level conversion for dual-supply systems
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) im...
Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic
EOR
2008
93views more  EOR 2008»
14 years 12 months ago
A survey of surface mount device placement machine optimisation: Machine classification
The optimisation of a printed circuit board assembly line is mainly influenced by the constraints of the surface mount device (SMD) placement machine and the characteristics of th...
Masri Ayob, Graham Kendall
GECCO
2003
Springer
129views Optimization» more  GECCO 2003»
15 years 5 months ago
Inherent Fault Tolerance in Evolved Sorting Networks
This poster paper summarizes our research on fault tolerance arising as a by-product of the evolutionary computation process. Past research has shown evidence of robustness emergin...
Rob Shepherd, James A. Foster
DAC
2005
ACM
16 years 24 days ago
A novel synthesis approach for active leakage power reduction using dynamic supply gating
: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hami...
FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
15 years 6 months ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung