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DAC
2005
ACM
16 years 25 days ago
Variations-aware low-power design with voltage scaling
We present a new methodology which takes into consideration the effect of Within-Die (WID) process variations on a low-voltage parallel system. We show that in the presence of pro...
Navid Azizi, Muhammad M. Khellah, Vivek De, Farid ...
ISPD
2005
ACM
145views Hardware» more  ISPD 2005»
15 years 5 months ago
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs
In this paper, we present a hierarchical ratio partitioning based placement algorithm for large-scale mixed-size designs. The placement algorithm consists of three steps: global p...
Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Ya...
FPGA
2008
ACM
129views FPGA» more  FPGA 2008»
15 years 1 months ago
Efficient ASIP design for configurable processors with fine-grained resource sharing
Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. ...
Quang Dinh, Deming Chen, Martin D. F. Wong
CF
2004
ACM
15 years 5 months ago
Designing and testing fault-tolerant techniques for SRAM-based FPGAs
This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable a...
Fernanda Lima Kastensmidt, Gustavo Neuberger, Luig...
DAC
2004
ACM
15 years 5 months ago
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
Philip Brisk, Adam Kaplan, Majid Sarrafzadeh