852 search results - page 7 / 171 » Categories, Allegories and Circuit Design |
247
Voted
DAC
2012
ACM
12 years 12 months ago
2012
ACM
We develop a projected-subgradient primal-dual Lagrange optimization for global placement, that can be instantiated with a variety of interconnect models. It decomposes the origin...
ICCAD
2009
IEEE
14 years 7 months ago
2009
IEEE
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...
109
Voted
JUCS
2007
14 years 9 months ago
2007
: It is a difficult problem that using cellular neural network to make up of analog signal processing circuit. This paper presented the architecture of new cellular neural network ...
DAC
2007
ACM
15 years 10 months ago
2007
ACM
A protocol for latency-insensitive design with early evaluation is presented. The protocol is based on a symmetric view of the system in which tokens carrying information move in ...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...