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DAC
2008
ACM
16 years 26 days ago
Enhancing timing-driven FPGA placement for pipelined netlists
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
Kenneth Eguro, Scott Hauck
GLVLSI
2008
IEEE
190views VLSI» more  GLVLSI 2008»
15 years 6 months ago
A low leakage 9t sram cell for ultra-low power operation
This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it i...
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
DAC
2006
ACM
15 years 5 months ago
SystemC transaction level models and RTL verification
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
Stuart Swan
DAC
2007
ACM
16 years 26 days ago
Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift
Statistical behavior of device leakage and threshold voltage shows a strong width dependency under microscopic random dopant fluctuation. Leakage estimation using the conventional...
Jie Gu, Sachin S. Sapatnekar, Chris H. Kim
DAC
2003
ACM
16 years 25 days ago
A new enhanced constructive decomposition and mapping algorithm
Structuring and mapping of a Boolean function is an important problem in the design of complex integrated circuits. Libraryaware constructive decomposition offers a solution to th...
Alan Mishchenko, Xinning Wang, Timothy Kam