852 search results - page 89 / 171 » Categories, Allegories and Circuit Design |
GLVLSI
2003
IEEE
15 years 5 months ago
2003
IEEE
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...
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DAC
2010
ACM
15 years 3 months ago
2010
ACM
Post-silicon validation is used to detect and fix bugs in integrated circuits and systems after manufacture. Due to sheer design complexity, it is nearly impossible to detect and ...
DAC
2005
ACM
15 years 1 months ago
2005
ACM
This paper presents an efficient hardware architecture of an on-chip logic minimization coprocessor. The proposed architecture employs TCAM cells to provide fastest and memory eï¬...
DAC
2005
ACM
15 years 1 months ago
2005
ACM
This paper presents a new test response compaction technique with any number of unknown logic values (X’s) in the test response bits. The technique leverages an X-tolerant respo...
ICFP
2008
ACM
15 years 12 months ago
2008
ACM
In efforts to overcome the complexity of the syntax and the lack of formal semantics of conventional hardware description languages, a number of functional hardware description la...