852 search results - page 9 / 171 » Categories, Allegories and Circuit Design |
GLVLSI
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
81
Voted
ISLPED
2004
ACM
15 years 2 months ago
2004
ACM
The principle of adiabatic switching in conventional energyrecovery adiabatic circuit is generally explained in literature with the help of the rudimentary RC circuit driven by a ...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated c...
GECCO
2008
Springer
14 years 10 months ago
2008
Springer
This paper proposes a new algorithm which promotes well distributed non-dominated fronts in the parameters space when a single-objective function is optimized. This algorithm is b...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient ...