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» Cell Broadband Engine processor: Design and implementation
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ICCAD
2002
IEEE
89views Hardware» more  ICCAD 2002»
15 years 6 months ago
Free space management for cut-based placement
IP blocks and large macro cells are increasingly prevalent in physical design, actually causing an increase in the available free space for the dust logic. We observe that top-dow...
Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia
ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
15 years 7 months ago
256-channel integrated neural interface and spatio-temporal signal processor
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...
GLVLSI
2005
IEEE
122views VLSI» more  GLVLSI 2005»
15 years 7 months ago
Thermal aware cell-based full-chip electromigration reliability analysis
A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-ba...
Syed M. Alam, Donald E. Troxel, Carl V. Thompson
ICCS
2009
Springer
14 years 11 months ago
Evaluating the Jaccard-Tanimoto Index on Multi-core Architectures
The Jaccard/Tanimoto coefficient is an important workload, used in a large variety of problems including drug design fingerprinting, clustering analysis, similarity web searching a...
Vipin Sachdeva, Douglas M. Freimuth, Chris Mueller
CHES
2009
Springer
230views Cryptology» more  CHES 2009»
16 years 2 months ago
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves
Abstract. This paper presents a design-space exploration of an applicationspecific instruction-set processor (ASIP) for the computation of various cryptographic pairings over Barre...
David Kammler, Diandian Zhang, Dominik Auras, Gerd...