324 search results - page 39 / 65 » Cell Broadband Engine processor: Design and implementation |
133
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CCECE
2006
IEEE
15 years 7 months ago
2006
IEEE
This paper presents a hardware/software co-design for Multi Protocol Label Switching (MPLS) using RSVP-TE as a signaling protocol. MPLS is the protocol framework on which the atte...
139
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SAMOS
2010
Springer
14 years 12 months ago
2010
Springer
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
108
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VLSID
2007
IEEE
16 years 1 months ago
2007
IEEE
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...
ARCS
2006
Springer
15 years 5 months ago
2006
Springer
: Given is the following "creature's exploration problem": n creatures are moving around in an unknown environment in order to visit all cells in shortest time. This...
DATE
2006
IEEE
15 years 7 months ago
2006
IEEE
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...