This paper surveys recent results in the area of virtual path layout in ATM networks. We present a model for the theoretical study of these layouts the model amounts to covering t...
—We envision that future FPGA will use a hardwired network on chip (HWNoC) [14] as a unified interconnect for functional communications (data and control) as well as configurat...
The explosive growth in the use of mobile devices coupled with users’ desires for real-time applications has provided new challenges in the design of protocols for mobile ad hoc...
Configurable on chip multiprocessor systems combine advantages of task-level parallelism and the flexibility of field-programmable devices to customize architectures for paralle...
Harold Ishebabi, Philipp Mahr, Christophe Bobda, M...
The problem of discriminating between two nite point sets in n-dimensional feature space by a separating plane that utilizes as few of the features as possible, is formulated as a...
Paul S. Bradley, Olvi L. Mangasarian, W. Nick Stre...