170 search results - page 14 / 34 » Challenges in Embedded Memory Design and Test |
185
Voted
FPGA
2004
ACM
15 years 7 months ago
2004
ACM
Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. Until recently, designers using FPGAs had le...
108
Voted
VLSID
2004
IEEE
16 years 3 months ago
2004
IEEE
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
132
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ISCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
126
Voted
VTS
2008
IEEE
15 years 9 months ago
2008
IEEE
Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a ro...
138
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CGO
2009
IEEE
15 years 10 months ago
2009
IEEE
Abstract—Multicore systems have not only become ubiquitous in the desktop and server worlds, but are also becoming the standard in the embedded space. Multicore offers programabi...