658 search results - page 25 / 132 » Challenges in Physical Chip Design |
JNCA
2007
14 years 9 months ago
2007
As the line rates standards are changing frequently to provide higher bit rates, the routers design has become very challenging due to the need for new wire-speed router’s netwo...
ASPDAC
2011
ACM
14 years 1 months ago
2011
ACM
Abstract— Three-dimensional (3D) integration and Networkon-Chip (NoC) are both proposed to tackle the on-chip interconnect scaling problems, and extensive research efforts have b...
FPL
2009
Springer
15 years 1 months ago
2009
Springer
This paper investigates the challenges of run-time resource management in future coarse-grained network-onreconfigurable-chips (NoRCs). Run-time reconfiguration is a key feature e...
FPGA
2004
ACM
15 years 1 months ago
2004
ACM
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...