658 search results - page 27 / 132 » Challenges in Physical Chip Design |
74
Voted
ICCAD
2007
IEEE
15 years 9 months ago
2007
IEEE
—We present an implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times. We ...
75
Voted
ENTCS
2008
15 years 26 days ago
2008
A Network-on-Chip (NoC) is increasingly needed to interconnect the large number and variety of Intellectual Property (IP) cells that make up a System-on-Chip (SoC). The network mu...
TVLSI
2010
14 years 7 months ago
2010
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
151
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DATE
2010
IEEE
15 years 5 months ago
2010
IEEE
Networks-on-Chip (NoCs) are a promising interconnect paradigm to address the communication bottleneck of Systems-on-Chip (SoCs). Wormhole flow control is widely used as the trans...
171
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CAL
2010
14 years 10 months ago
2010
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by...